Join Google Cloud and shape the future of AI/ML hardware acceleration by driving TPU technology. This role offers the chance to develop custom silicon solutions that power Google's most demanding AI/ML applications and contribute to the innovation behind globally loved products. Leverage your design and verification expertise to validate complex digital designs, focusing on TPU architecture within AI/ML-driven systems.

The AI and Infrastructure team is at the forefront of innovation, empowering Google customers with breakthrough capabilities. We deliver AI and Infrastructure at unparalleled scale, efficiency, and reliability, serving Googlers, Google Cloud customers, and billions of users worldwide. We are the engine behind Google's groundbreaking advancements, enabling AI model development, providing immense computing power, and offering essential platforms for developers.

Our team is instrumental in shaping world-leading hyperscale computing. Key areas include TPU development, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, and systems research, among others.

Collaborate with architecture and silicon engineering teams to craft next-generation DFT/DFX features for large-scale SoCs. Design and implement robust software and hardware validation solutions for advanced testing, encompassing logic BIST (LBIST), memory BIST (MBIST), and Scan compression. Pioneer research and development of machine learning or semi-analytical models to address intricate DFT challenges. Effectively triage, debug, and resolve critical post-silicon yield and structural failures through advanced failure analysis (FA) and volume diagnostics. Author and meticulously review technical specifications for SoC testability, while fostering strong partnerships with EDA vendors.

A PhD degree in Electronics and Communication Engineering, Electrical Engineering, Computer Engineering, or a closely related technical field is required, or equivalent practical experience.

Demonstrated experience with programming languages such as C++, Python, and Verilog, alongside proficiency in Synopsys and Cadence tools.

Preferred qualifications include 2 years of Silicon Engineering experience post PhD. Expertise with Electronic Design Automation (EDA) tools spanning design, verification, DFT, and implementation is highly valued. Strong knowledge of Design for Test (DFT) concepts, including Boundary Scan, ATPG, and MBIST, is essential.