Shape the future of AI/ML hardware acceleration by driving TPU technology that powers Google's most demanding applications. Join a team pushing boundaries in developing custom silicon solutions for Google's TPUs. Leverage your design and verification expertise to verify complex digital designs, focusing on TPU architecture and its integration within AI/ML-driven systems.

The AI and Infrastructure team redefines possibilities, empowering Google customers with breakthrough capabilities and insights through AI and Infrastructure at unparalleled scale and efficiency. We are the driving force behind Google's groundbreaking innovations, enabling the development of AI models and delivering computing power to global services.

Collaborate with architecture and silicon engineers to develop next-generation DFT/DFX features for large-scale SoCs. Design and implement software and hardware validation solutions for advanced testing, including logic BIST, memory BIST, and Scan compression. Research, develop, and integrate machine learning models to address complex DFT challenges. Triage, debug, and resolve high-priority post-silicon yield and structural failures by driving advanced failure analysis and volume diagnostics. Write and review technical specifications for SoC testability, partnering with EDA vendors.

Requires a PhD degree in Electronics and Communication Engineering, Electrical Engineering, Computer Engineering, or a related technical field, or equivalent practical experience. Possess experience in programming languages such as C++, Python, and Verilog, along with proficiency in Synopsys and Cadence tools.

Preferred qualifications include 2 years of Silicon Engineering experience post PhD, and familiarity with Electronic Design Automation (EDA) tools for design, verification, DFT, and implementation. Essential knowledge includes Design for Test (DFT) concepts like Boundary Scan, ATPG, and MBIST.