Shape the future of AI/ML hardware acceleration by driving TPU technology for Google's demanding applications. Join a team dedicated to developing custom silicon solutions that power Google's TPUs and contribute to innovations used by millions worldwide.

This role involves leveraging your design and verification expertise to ensure the integrity of complex digital designs, with a particular focus on TPU architecture and its seamless integration within AI/ML-driven systems. Be a part of a team redefining what's possible, empowering Google customers with cutting-edge capabilities at unparalleled scale, efficiency, and reliability.

Collaborate with architecture and silicon engineers to design next-generation DFT/DFX features for large-scale SoCs. Develop robust software and hardware validation solutions for advanced testing, including logic BIST, memory BIST, and scan compression. Research and implement machine learning or semi-analytical models to tackle intricate DFT challenges. Analyze, debug, and resolve critical post-silicon yield and structural failures by leading advanced failure analysis and volume diagnostics. Author and meticulously review technical specifications for SoC testability, fostering strong partnerships with EDA vendors.

A PhD degree in Electronics and Communication Engineering, Electrical Engineering, Computer Engineering, or a related technical field is required. Equivalent practical experience will also be considered.

Proficiency in programming languages such as C++, Python, and Verilog is essential, along with hands-on experience with Synopsys and Cadence tools.

Preferred qualifications include two years of Silicon Engineering experience post-PhD and familiarity with Electronic Design Automation (EDA) tools across design, verification, DFT, and implementation.

Essential knowledge of Design for Test (DFT) principles, including Boundary Scan, ATPG, and MBIST, is expected.