Join a forward-thinking team dedicated to crafting bespoke silicon solutions that drive the innovation behind Google's direct-to-consumer products. You will be instrumental in shaping groundbreaking products enjoyed by millions globally. Your expertise will define the next generation of hardware, delivering exceptional performance, efficiency, and seamless integration.

The AI and Infrastructure team is at the forefront of technological advancement. We empower Google customers by providing AI and Infrastructure solutions at an unprecedented scale, characterized by efficiency, reliability, and speed. Our reach extends to Googlers, Google Cloud clients, and billions of users worldwide.

We are the engine powering Google's most significant innovations. Our teams are responsible for developing cutting-edge AI models, delivering unmatched computing power for global services, and building the foundational platforms that enable developers to create the future. From intricate software to robust hardware, our collective efforts are shaping the landscape of world-leading hyperscale computing. Key areas of focus include the development of TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, and systems research, among many others.

Develop and maintain comprehensive documentation for Design for Testability (DFT) architecture and test sequences, including boot-up protocols for test pins.

Integrate DFT logic, such as scan and BIST, at both Register-Transfer Level (RTL) and netlist stages.

Conduct thorough DFT checks to ensure scan coverage and validate memory Built-In Self Test (BIST) functionality.

Spearhead DFT planning for SoC/IP/Subsystems (SS) and foster collaboration with cross-functional teams. Develop DFT constraints to aid timing closure and provide essential support for Physical Design (PD) and Static Timing Analysis (STA).

Execute quality assurance flows, including Lint and Clock Domain Crossing (CDC) checks, for DFT RTL within DFT modes. Actively participate in design debugging and code reviews in close coordination with other IPs' Design Verification (DV) and Physical Design teams.

A Bachelor's degree in Electrical Engineering or a comparable field is essential, or demonstrable equivalent practical experience.

Possess at least two years of hands-on experience in analog or mixed-signal Integrated Circuit (IC) design.

Demonstrate experience with system-on-chip (SoC) design and integration workflows, alongside proficiency in design automation tools.

Exhibit expertise in Design for Test (DFT) technologies, including Scan, Algorithmic Test Pattern Generation (ATPG), and Memory Built-In Self Test (MBIST).

Showcase practical experience with Application-Specific Integrated Circuit (ASIC) DFT synthesis, Static Timing Analysis (STA), simulation, and the overall verification process.

Preferred qualifications include a Master's degree or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related discipline.

Valuable experience working alongside Automatic Test Equipment (ATE) engineers, encompassing silicon bring-up, pattern generation, debug, validation on ATE, and troubleshooting silicon issues is highly regarded.

Experience within System on a Chip (SoC) lifecycles, including silicon bring-up and debug activities, is beneficial.

Familiarity with fault modeling techniques is a plus.