Join a forward-thinking team dedicated to developing custom silicon solutions that will power Google's future direct-to-consumer products. You'll be instrumental in shaping the innovation behind beloved products, influencing the next generation of hardware experiences with unparalleled performance, efficiency, and integration.

The AI and Infrastructure team is at the forefront of redefining possibilities. We provide Google customers with groundbreaking capabilities and insights, delivering AI and Infrastructure at immense scale, efficiency, reliability, and velocity. Our reach extends to Googlers, Google Cloud customers, and billions of Google users globally.

We are the engine behind Google's transformative innovations. Our work empowers the development of cutting-edge AI models, provides immense computing power to global services, and creates essential platforms for developers building the future. Across software and hardware, our teams are shaping world-leading hyperscale computing, with key contributions to TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, and systems research.

Optimize and simulate clock tree networks, meticulously analyzing key clock quality metrics.

Evaluate various clock Intellectual Property (IP) components, including PLLs, FLLs, adaptive systems incorporating ADCs, clock drivers, receivers, and differential buffers.

Conduct comprehensive jitter compliance simulations for Serdes, PCIe reference clocks, and other high-speed clocking systems.

Provide expert guidance to sub-system clocking teams on best practices for clock quality assurance.

Collaborate closely with timing and sign-off teams, offering crucial inputs on clock characteristics such as jitter, duty-cycle, and aging margins.

A Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience is required.

Possess at least 4 years of hands-on experience in mixed-signal analog integrated circuit design or equivalent practical expertise.

Demonstrated experience with analog circuits, simulation methodologies, clocking systems, and general analog design principles.

Preferred qualifications include a Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, with a specialization in computer architecture.