Join a pioneering team shaping custom silicon solutions that will define the future of Google's consumer products. You will be instrumental in driving innovation for products enjoyed by millions globally.

Your expertise will be key in crafting next-generation hardware, focusing on delivering exceptional performance, efficiency, and seamless integration. The AI and Infrastructure team is dedicated to expanding the frontiers of possibility, empowering Google users and customers with advanced capabilities and insights through AI and Infrastructure at an unprecedented scale, efficiency, and reliability.

Our contributions are vital for Google's groundbreaking advancements, fueling the development of sophisticated AI models, providing immense computing power for worldwide services, and establishing the foundational platforms for developers. Our teams span software and hardware, influencing the evolution of world-leading hyperscale computing, with significant efforts in TPUs, Google Cloud's Vertex AI, Google Global Networking, Data Center operations, and systems research.

Key responsibilities include simulating and optimizing clock tree networks to meet critical clock quality metrics. You will evaluate various clock IPs such as PLLs and FLLs, and other adaptive systems including ADCs, clock drivers, receivers, and differential buffers.

This role involves conducting detailed jitter compliance simulations for Serdes, PCIe reference clocks, and other high-speed clocking applications. You will also guide sub-system clocking teams on best practices for clock quality and provide essential input to timing and sign-off teams regarding clock characteristics like jitter, duty-cycle, and aging margins.

We are seeking candidates with a Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related discipline, or equivalent practical experience. A minimum of 4 years of hands-on experience in mixed-signal analog integrated circuit design, or equivalent practical experience, is required.

Experience with analog circuits, simulation methodologies, clocking architectures, and general analog design principles is essential. Preferred qualifications include a Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, with a specialization in computer architecture.