NVIDIA is a leader in transforming computer graphics, PC gaming, and accelerated computing. Join our team and be at the forefront of AI-driven innovation, defining the next era of computing. We are seeking driven and imaginative individuals for our automotive verification group to shape the future of automotive chips and systems. This role offers direct experience with high-performance CPUs, memory subsystems, interconnect fabrics, high-speed I/Os, and advanced Tegra chip technologies.

As an NVIDIAN, you'll be part of a diverse and supportive environment, inspired to do your best work and make a lasting global impact. We are committed to fostering an inclusive workplace where everyone can thrive and contribute their unique talents.

As the owner of HSIO IP's unit level verification, you will develop UVM-based verification test benches and methodologies. Your responsibilities will include architecting testbenches, crafting verification environments using SystemVerilog and UVM, and defining test plans for modules, clusters, and systems.

You will build efficient and reusable bus functional models, monitors, checkers, and scoreboards. Implementing functional coverage and coordinating verification closure for your unit are key. Collaboration with architects, designers, FPGA, and post-silicon teams is essential to ensure unit robustness.

A B.Tech or M.Tech degree in ECE, EE, CSE, or an equivalent is required. Candidates must possess over 4 years of proven experience in verification closure for complex units, subsystems, or SOC-level verification. Demonstrated expertise in High-Speed IO verification (UFS/PCIE/XUSB) and knowledge of 10G/1G Ethernet MAC and Switch are essential.

Proficiency in the latest verification methodologies like SystemVerilog and UVM is expected. Strong debugging and analytical skills, coupled with experience in industry-standard verification tools, are crucial. Excellent interpersonal and communication skills are necessary to collaborate effectively with global teams in a matrix organization.