Join NVIDIA and contribute to the future of automotive chips and systems. This role offers hands-on experience with high-performance computing, memory subsystems, interconnect fabrics, and advanced Tegra chip technologies. We are looking for enthusiastic and imaginative individuals to drive innovation in our automotive verification group, specifically focusing on HSIO IP cluster and SOC verification.

NVIDIA is a leader in transforming computer graphics, PC gaming, and accelerated computing, now at the forefront of AI. Become an NVIDIAN and be part of a diverse, supportive environment where innovation thrives and individuals make a lasting impact.

Architect and develop verification components and APIs for cluster and system-level testbenches. Verify complex rapid data transfer IO IPs and subsystems like USB, UFS, MPHY, Ethernet, and MACSEC.

Key responsibilities include: - Architecting testbenches and verification environments using SV and C/C++. - Defining test plans, tests, and verification infrastructure for clusters and systems. - Building efficient and reusable bus functional models, monitors, checkers, and scoreboards. - Implementing functional coverage and ensuring SOC-level verification closure. - Collaborating with architects, designers, FPGA, and post-silicon teams.

A B.Tech or M.Tech degree in ECE, EE, CSE, or an equivalent qualification is essential. We require over 5 years of experience in verification closure for complex units, subsystems, or SOC levels.

Candidates should possess: - Proven experience in High-Speed IO verification (UFS/PCIe/XUSB). - Knowledge of 10G/1G Ethernet MAC and Switch. - Proficiency in the latest verification methodologies like SV and UVM. - Strong debugging and analytical skills, with experience in industry-standard verification tools. - Excellent interpersonal and communication skills for effective collaboration in global, cross-cultural teams.