Join NVIDIA's Silicon Co-Design Group (SCG) and shape the future of computing across diverse markets including Datacenter, Gaming, Robotics, Automotive, and Embedded systems. SCG is pivotal in bridging architecture, design, marketing, operations, and productization. System Integration at SCG is where all decisions converge, tackling critical challenges that ensure product success. This is an opportunity to work on high-impact silicon programs and make a significant difference in product delivery.

We are seeking a Senior System Integration and Validation Engineer to lead critical system validation and debug efforts. Your expertise will be vital in ensuring the smooth execution of our flagship GPU, SoC, and platform programs. This role offers the chance to address complex, multi-team failures and drive them to resolution, directly impacting our milestone achievements.

As a Senior Engineer, you will own the end-to-end system validation for NVIDIA's GPU, SoC, and platform programs, encompassing feature verification, PVT stress, large-scale system stress campaigns, and multi-unit fleet testing.

You will lead the debug of the most challenging cross-stack issues, spanning logic, signal integrity, power delivery, firmware, and software interactions, driving them to root cause with robust workarounds and productized fixes.

Develop comprehensive test plans, scripts, and automation for next-generation chips, translating architectural requirements, boot flows, high-speed I/O, and power/thermal dependencies into executable coverage. Design and deploy AI-enabled debug and validation workflows, incorporating essential guardrails like evaluations, regression validation, and false-positive handling to enhance cycle time, debug velocity, and escape rate.

Translate complex silicon and system risks into actionable insights for technical and executive audiences. Partner with globally distributed teams, including counterparts in India and other major hubs, across silicon design, DFT, firmware, software, manufacturing, and platform engineering. Lead crisis-mode debug task forces and institutionalize learnings into reusable methodologies for adjacent programs. Proactively identify critical silicon and platform issues before they reach customers by shifting validation left with system stress and feature-interaction tests. Build AI-enabled validation into a tangible capability, deploying debug, triage, and root-cause hypothesis generation workflows with the necessary guardrails to ensure production readiness.

A Bachelor's or Master's degree in Electronics, Electrical, or Computer Engineering, or an equivalent field, coupled with a minimum of 6 years of post-silicon validation, system integration, or platform debug experience on shipped GPU, CPU, or SoC products is required.

Demonstrate hands-on debug expertise across silicon, board, and software interfaces, including logic design, signal integrity, power delivery, high-speed I/O, and PVT behavior. Strong fundamentals in Electrical Engineering, particularly SI/PI, power delivery, and thermal management, along with a working understanding of GPU, CPU, or SoC architectures in PC, Datacenter, or Automotive contexts, are essential.

Provide at least one specific instance of successfully taking an ambiguous, multi-team failure to root-cause closure with a productized fix, and a proven track record of leading a project team through a critical crisis, making key decisions.

Showcase a demonstrated AI-driven validation workflow that you either built or scaled, with adoption beyond personal use and measurable impact on debug velocity, coverage, or escape rate. Be prepared to detail the guardrails implemented and the potential risks associated with AI in your workflows.