Join NVIDIA's innovative Digital IP group as a Senior SRAM Circuit Design Engineer. This role offers a high-visibility position focused on developing sophisticated SRAM compilers crucial for NVIDIA's cutting-edge chip designs. You'll be instrumental in creating advanced IP that powers products changing the world.

NVIDIA is at the forefront of technological advancement, from pioneering GPUs to leading the AI revolution. We foster a diverse and supportive environment where innovation thrives. Become part of a team dedicated to amplifying human creativity and intelligence through impactful work.

Engage in transistor-level embedded SRAM design, including layout supervision, physical and logical verification, and debugging of SRAM macros.

Contribute to SRAM compiler development by conceptualizing, defining, and coding efficient automation for simultaneous assembly and validation of multiple unique SRAM macros.

Explore future process nodes, developing techniques for optimal power, performance, and area characteristics.

Collaborate with SOC design partners to meet performance and cost objectives, guide silicon test and characterization, and support productization for demanding real-world applications.

Requires a BSEE degree (or equivalent experience), with an MSEE or PhD preferred. A minimum of 5 years of SRAM design experience is essential, alongside a strong foundation in digital circuit design, layout, and validation on advanced FinFET processes.

Experience with single-port, dual-port, or register file SRAM-based macros is mandatory, including complex circuits like self-timed logic and sense-amplifiers.

Proficiency in Python scripting for data parsing and task automation is necessary. A proven track record of delivering designs to production is a key requirement.

Stand-out candidates will possess strong self-motivation, meticulous attention to detail, and excellent communication skills. Familiarity with Cadence tools and silicon testing/debug experience is advantageous.