Join NVIDIA's innovative Digital IP (DIP) group as a Senior SRAM Circuit Design Engineer and contribute to cutting-edge silicon development. This high-visibility role involves designing sophisticated SRAM compilers crucial for NVIDIA's advanced chips. Be part of a team that pushes the boundaries of technology, shaping the future of AI, graphics, and parallel computing.

NVIDIA is a dynamic, learning-focused organization. We thrive on tackling complex challenges and making a global impact. Immerse yourself in a supportive and diverse environment where your best work is inspired and valued. Come amplify human creativity and intelligence with us.

As an SRAM Circuit Designer, you will engage in transistor-level circuit design for embedded SRAM macros, overseeing layout implementation and performing thorough physical and logical verification. You will also contribute to SRAM compiler development, conceptualizing and coding efficient methods to automate the assembly and validation of unique SRAM macros.

Furthermore, this role involves exploring future process nodes to achieve optimal power, performance, and area. You will collaborate closely with SOC design, silicon test, and productization teams, guiding them to meet performance and cost objectives, and ensuring silicon readiness for demanding real-world applications.

We are seeking candidates with a minimum BSEE or equivalent experience, with an MSEE or PhD preferred. A strong foundation in digital circuit design, layout, and validation on advanced FinFET processes is essential, with at least 3 years of dedicated SRAM design experience.

Prior experience with single-port, dual-port, or register file SRAM-based macros is required, including familiarity with complex circuits like self-timed logic and sense-amplifiers. Proficiency in Python for data parsing and task automation, along with a proven track record of delivering designs to production, are necessary. Standout candidates will possess strong self-motivation, attention to detail, excellent communication skills, and scripting expertise. Familiarity with Cadence tools and silicon testing/debug experience are advantageous.