NVIDIA is a dynamic and evolving organization dedicated to pushing the boundaries of what's possible. We are seeking a skilled and creative Senior SRAM Circuit Design Engineer to join our Digital IP (DIP) group. This high-visibility role is crucial for developing sophisticated SRAM compilers that are integral to NVIDIA's advanced chip designs.

As part of the DIP team, you will collaborate closely with internal SOC design, silicon testing, and productization teams. You will contribute to creating IP that powers groundbreaking products, driving innovation and shaping the future of technology. Join us to amplify human creativity and intelligence in a supportive and diverse environment.

Your responsibilities will encompass embedded SRAM design, including transistor-level circuit design, layout implementation supervision, and both physical and logical verification. You will also be involved in debugging SRAM macros.

A key aspect of this role is SRAM compiler development, where you will envision, define, and code efficient methods for automating the assembly and validation of multiple unique SRAM macros using NVIDIA's extensive compute resources.

Furthermore, you will explore future process nodes, developing techniques for optimal power, performance, and area. Guiding SOC design, silicon test, and productization efforts by collaborating with partners to achieve performance and cost goals is also integral to the position.

We require a minimum of a BSEE or equivalent experience, with an MSEE or PhD being preferred. Candidates must possess 3+ years of SRAM design experience, complemented by a strong foundation in digital circuit design, layout, and validation on advanced FinFET processes.

Prior design experience with single-port, dual-port, or register file SRAM-based macros is essential, including expertise in complex circuits like self-timed logic and sense-amplifiers. Proficiency in Python scripting for data parsing and task automation is also necessary, along with a proven track record of delivering designs to production.

Standout candidates will demonstrate strong self-motivation, meticulous attention to detail, and excellent communication skills. Familiarity with Cadence schematic and layout tools, as well as silicon testing/debug experience, would be advantageous.