Join a dynamic team at Google Cloud, where you'll contribute to developing cutting-edge custom silicon solutions that power our direct-to-consumer products and data center accelerators. This role is crucial in shaping the future of hardware, delivering exceptional performance, efficiency, and integration for products used by millions worldwide.

Your work will be instrumental in advancing machine learning computation through the design of Application-Specific Integrated Circuits (ASICs). You will collaborate closely with Architecture, Verification, Power and Performance, and Physical Design teams to ensure the delivery of high-quality designs for next-generation accelerators. A key aspect of this position involves solving complex technical challenges through micro-architecture innovation and carefully evaluating design trade-offs.

As a Senior SoC RTL Design Engineer, you will take ownership of the microarchitecture and implementation of Internet Protocols (IPs) and subsystems. You'll partner with Architecture, Firmware, and Software teams to drive feature closure and craft detailed micro-architecture specifications.

This role also involves leading design methodology advancements, libraries, debugging, and code reviews in coordination with other IP Design Verification (DV) and physical design teams. A significant focus will be on identifying and implementing improvements in power, performance, and area (PPA) for the designed IPs.

We are seeking experienced engineers with a strong foundation in digital logic design principles and RTL design concepts. A minimum of 8 years of experience with languages like Verilog or SystemVerilog is required.

Essential qualifications include a Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. Proficiency in logic synthesis for RTL code optimization, performance, and power improvement, along with experience in low-power design techniques, is critical for this role.