Join Google Cloud and contribute to the evolution of AI/ML hardware acceleration. This role focuses on pioneering TPU (Tensor Processing Unit) technology that drives Google's most demanding AI/ML applications. Be part of a team pushing boundaries in custom silicon development for Google's TPUs. Leverage your expertise in design and verification to ensure the reliability of complex digital designs, particularly TPU architecture and its integration within AI/ML systems. This is an opportunity to shape the future of world-leading hyperscale computing.

The AI and Infrastructure team is at the forefront of innovation, delivering AI and Infrastructure at unparalleled scale and efficiency. We empower Google customers, Googlers, and billions of users worldwide with breakthrough capabilities. Our work spans software and hardware, including the development of TPUs, Vertex AI for Google Cloud, and global networking infrastructure.

Take ownership of the entire verification life-cycle, from initial planning and test execution through to coverage closure, with a strong focus on meeting stringent AI/ML performance and accuracy targets. Develop robust constrained-random verification environments using SystemVerilog and UVM to uncover corner-case bugs and guarantee the reliability of AI/ML workloads on TPU hardware. Collaborate closely with design and verification engineers on active projects to perform comprehensive verification.

Key responsibilities include: - Planning the verification of digital design blocks. - Collaborating with design engineers to define critical verification scenarios. - Creating and implementing various coverage measures for stimulus and edge cases. - Debugging tests alongside design engineers to ensure functionally correct design blocks. - Measuring verification progress and identifying gaps towards tape-out. - Building constrained-random verification environments utilizing SystemVerilog and UVM.

This position requires a Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, coupled with 8 years of experience in digital logic verification at the RTL level using SystemVerilog or Specman/E for FPGAs or ASICs. Experience in verifying IP/subsystem/SoCs within the Networking domain, including packet processing, bandwidth management, and congestion control, is highly desirable. Familiarity with verifying digital systems using standard IP components and interconnects, such as microprocessor cores and hierarchical memory subsystems, is also crucial.

Preferred qualifications include a Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, with a specialization in computer architecture. Experience with industry-standard simulators, revision control systems, and regression systems is beneficial. Prior experience with AI/ML accelerators or vector processing units, and a comprehensive understanding of the full verification life cycle, are also valued. Excellent problem-solving and communication skills are essential.