Join a pioneering team developing custom silicon solutions that will power the future of Google's direct-to-consumer products. Your expertise will be instrumental in shaping next-generation hardware experiences, delivering exceptional performance, efficiency, and integration for products used by millions globally.

This role is part of the AI and Infrastructure team, dedicated to redefining possibilities. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, and reliability. Our impact extends from internal Googlers to Google Cloud customers and billions of users worldwide.

We are the driving force behind Google's groundbreaking innovations, enabling cutting-edge AI models, providing immense computing power to global services, and building essential platforms for developers. Our teams are shaping the future of world-leading hyperscale computing, focusing on areas like TPUs, Vertex AI for Google Cloud, Google Global Networking, and data center operations.

Define and champion the implementation of advanced physical design methodologies.

Take full ownership of assigned physical design partitions or the top-level design.

Strategically manage and optimize the timing and power consumption of the design.

Actively contribute to the enhancement of design methodologies, libraries, and conduct thorough code reviews.

Establish clear physical design-related rule sets for functional design engineers to ensure adherence and quality.

A Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a closely related field, or equivalent practical experience is required.

Possess a minimum of 8 years of experience in advanced design aspects, including clock/voltage domain crossing, design for testing (DFT), and low power designs.

Demonstrate experience with system on a chip (SoC) cycles and the complete SoC design flow.

Have proven experience in high-performance, high-frequency, and low-power design domains.

Preferred qualifications include a Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, with a specialization in computer architecture. Experience with coding in System Verilog and scripting in TCL, as well as familiarity with layout verification and design rules, are highly beneficial. Experience with very large scale integration (VLSI) in SoC or multiple ASIC design cycles is also advantageous.