Join a pioneering team developing cutting-edge custom silicon solutions that drive Google Cloud's AI and Infrastructure advancements. You will contribute to innovative hardware experiences, ensuring unparalleled performance and efficiency for products used by billions globally. Shape the future of hyperscale computing with your expertise.

This role is integral to redefining possibilities within AI and Infrastructure, empowering Google customers with breakthrough capabilities. Our team delivers AI and Infrastructure at scale, ensuring efficiency, reliability, and velocity for Googlers, Google Cloud customers, and end-users worldwide. We are the engine behind Google's groundbreaking innovations, from AI models to global services.

Define and implement advanced physical design methodologies. Take ownership of critical physical design partitions or the top-level integration. Effectively manage the timing and power consumption of complex designs. Contribute to the enhancement of design methodologies, libraries, and code review processes. Establish clear physical design rule sets for functional design engineers.

A Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience is required. Possess at least 8 years of experience in advanced design areas, including clock/voltage domain crossing, DFT, and low power designs. Familiarity with system on a chip (SoC) cycles is essential. Experience in high-performance, high-frequency, and low-power designs is a must.

Preferred qualifications include a Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, with a focus on computer architecture. Experience with System Verilog, TCL scripting, layout verification, design rules, and very large scale integration (VLSI) in SoC or ASIC design is highly beneficial.