Join a pioneering team developing custom silicon solutions that power Google's direct-to-consumer products and drive the future of AI infrastructure.

You will contribute to groundbreaking innovations, shaping next-generation hardware experiences with unparalleled performance, efficiency, and integration.

Our AI and Infrastructure team redefines possibilities, empowering Google customers with breakthrough capabilities at an unprecedented scale. We are the engine behind cutting-edge AI models and provide essential platforms for developers.

Lead the definition and execution of physical design methodologies.

Assume responsibility for physical design partitions or the top level.

Effectively manage the timing and power consumption of complex designs.

Contribute to enhancing design methodologies, libraries, and code quality through reviews.

Establish physical design rule sets for functional design engineers.

A Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related discipline, or equivalent practical experience, is required.

Possess a minimum of 8 years of experience in advanced design, including clock/voltage domain crossing, design for testing (DFT), and low-power designs.

Demonstrated experience within system on a chip (SoC) cycles is essential.

Proven expertise in high-performance, high-frequency, and low-power design environments.

Preferred qualifications include a Master's degree or PhD in relevant engineering fields, with expertise in System Verilog, TCL scripting, layout verification, and VLSI design for ASICs.