Join a pioneering team at Google Cloud, crafting custom silicon solutions that drive the future of Google's consumer products. You will be instrumental in shaping next-generation hardware, delivering exceptional performance, efficiency, and integration for products used by millions globally.

As a Physical Design Engineer, you'll collaborate with cross-functional teams, including functional design, DFT, architecture, and packaging. Your role involves solving complex technical challenges through innovative micro-architecture and logic circuit solutions, while optimizing for performance, power, and area.

The AI and Infrastructure team is at the forefront of innovation, empowering Google customers with advanced capabilities and insights. We deliver AI and Infrastructure at unparalleled scale, ensuring efficiency, reliability, and velocity for internal users, Google Cloud customers, and billions of global users. We are the engine behind Google's groundbreaking advancements, from cutting-edge AI models and unmatched computing power to foundational platforms enabling developers worldwide. Our work spans software to hardware, including TPUs, Vertex AI for Google Cloud, Global Networking, Data Center operations, and systems research.

Define and champion the implementation of advanced physical design methodologies. Take full ownership of critical physical design partitions or the top-level design. Proactively manage and optimize the timing and power consumption of the design. Contribute significantly to design methodology improvements, library development, and code reviews. Establish clear physical design-related rule sets for functional design engineers to adhere to.

Requires a Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related discipline, or equivalent practical experience. Must possess 8 years of in-depth experience in advanced design areas such as clock/voltage domain crossing, Design for Testing (DFT), and low-power design techniques. Demonstrated experience with system on a chip (SoC) design cycles is essential. Proven expertise in high-performance, high-frequency, and low-power design environments.

Preferred qualifications include a Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, with a specialization in computer architecture. Experience in coding with System Verilog and scripting with TCL is highly desirable. Familiarity with layout verification and design rules is a plus. Extensive experience with very large scale integration (VLSI) design within SoC environments or multiple SoC ASIC design cycles is advantageous.