Join a pioneering team at Google Cloud, shaping the future of custom silicon for direct-to-consumer products. Your work will directly influence the next generation of hardware, delivering exceptional performance, efficiency, and integration for innovations used by millions globally. This role is central to redefining possibilities within AI and Infrastructure, empowering Google customers with scalable, reliable, and efficient breakthrough capabilities.

This role involves defining and implementing physical design methodologies, taking ownership of design partitions or top-level integration. You will meticulously manage the timing and power consumption of the design, contributing to methodology improvements, libraries, and code reviews. A key responsibility includes establishing physical design rule sets for functional design engineers.

A Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, alongside 8 years of advanced design experience, is required. This includes expertise in clock/voltage domain crossing, design for testing (DFT), and low-power designs. Experience with system-on-chip (SoC) cycles and high-performance, high-frequency, low-power designs is essential. A Master's or PhD in a related field, with computer architecture focus, and proficiency in System Verilog and TCL scripting are preferred.