Shape the future of Google's direct-to-consumer products by joining a team dedicated to developing advanced custom silicon solutions. You'll play a crucial role in creating hardware experiences that delight millions globally, focusing on unparalleled performance, efficiency, and seamless integration.

This role is within the AI and Infrastructure team, which is at the forefront of innovation. We empower Google customers with cutting-edge capabilities and insights through AI and Infrastructure delivered at an unprecedented scale and efficiency. Our work impacts Googlers, Google Cloud customers, and billions of users worldwide, driving advancements in AI models, global computing power, and developer platforms.

Define and champion physical design methodologies throughout the implementation process. Take full ownership of specific physical design partitions or the entire top-level design. Proactively manage and optimize the timing and power consumption of the design. Actively contribute to design methodology improvements, library enhancements, and code reviews. Establish and communicate clear physical design rule sets for functional design engineers.

A Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, alongside equivalent practical experience, is required. Possess at least 8 years of hands-on experience in advanced design techniques, including clock/voltage domain crossing, Design for Testing (DFT), and low-power designs. Demonstrated experience with system on a chip (SoC) cycles. Proven expertise in high-performance, high-frequency, and low-power design methodologies.

Preferred qualifications include a Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, with a specialization in computer architecture. Experience with System Verilog coding and TCL scripting is advantageous. Familiarity with layout verification and adherence to design rules is beneficial. Experience in very large scale integration (VLSI) design within SoC environments or multiple SoC ASIC design cycles is highly valued.