Shape the future of AI/ML hardware acceleration by driving cutting-edge TPU technology. This role focuses on developing custom silicon solutions for Google's advanced AI/ML applications and Google's most demanding AI/ML applications. You will be instrumental in creating innovative micro-architecture and practical logic solutions for next-generation data center accelerators, with a particular emphasis on TPU architecture integration within AI/ML-driven systems.

The AI and Infrastructure team is at the forefront of redefining technological possibilities. We empower Google customers with breakthrough capabilities and insights through AI and Infrastructure delivered at unparalleled scale, efficiency, and reliability. Our contributions support Googlers, Google Cloud customers, and billions of Google users worldwide, driving innovation across hardware and software, including TPUs and Vertex AI for Google Cloud.

Define and develop high-quality RTL for memory controller frontends, guiding trade-offs in performance, area, power, timing, and configurability. Lead the design, integration, and delivery of complex memory controller backends and HBM/DDR PHY macros, ensuring quality from concept to tapeout. Collaborate with DV teams to build test plans, enhance coverage, and validate design intent using UVM and emulation, while staying current with JEDEC specifications and HBM trends.

Oversee ATE testing, first-silicon lab bring-up, and physical characterization of HBM PHY and controller across various PVT corners. Provide technical guidance and mentorship to junior engineers, fostering best practices in RTL design, review, documentation, and systematic root-cause debug.

A Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience, is required. A minimum of 10 years of experience in memory subsystem design, integration, or verification is essential. Expertise in DRAM protocols like HBM2e/HBM3/HBM4 or DDR/LPDDR4x/5/5X, including JEDEC timing, refresh, and training sequences, is critical. Proficiency in the DFI controller-to-PHY interface, experience leading feature or IP block development, and mentoring engineers are necessary.

Candidates must possess experience in SystemVerilog RTL, simulation, and debug flows. Preferred qualifications include a Master's or PhD in a relevant field with a focus on computer architecture, experience delivering configurable and reusable IP, and familiarity with integrating third-party controller and PHY IP. Experience with SECDED, Reed-Solomon error correction, UVM methodology, emulation-based pre-silicon validation, memory telemetry, and Silicon Lifecycle Management (SLM) are highly desirable.