Join Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) and contribute to powering Microsoft’s “Intelligent Cloud” mission. SCHIE is at the forefront of delivering core infrastructure and foundational technologies for over 200 Microsoft online businesses, including Azure, Office 365, and Xbox Live.

Within SCHIE, the Compute Silicon & Manufacturing Engineering (CSME) organization designs, develops, manufactures, and packages Microsoft's advanced computer chips, such as the Azure Cobalt. Our innovative solutions offer a significant strategic advantage to Microsoft and empower our customers to achieve more.

As the cloud business expands, timely, high-volume, high-quality, and cost-effective deployment of new offerings and hardware infrastructure is critical. The DFX (Design for Test & Debug) team plays a vital role in establishing operational success metrics for hardware manufacturing, enhancing planning processes, and improving quality, delivery, scale, and sustainability for Microsoft's cloud hardware. We are seeking experienced engineers passionate about customer-focused solutions, possessing deep industry insight, to envision and implement future technical solutions for managing and optimizing cloud infrastructure.

As a Senior Silicon Engineer-DFT, you will be entrusted with key responsibilities including:

- Owning block-level DFT architecture, specifications, and implementation for both logic and memory test solutions. - Driving DFT timing closure and signoff across various modes such as Scan, MBIST, LBIST, IJTAG, and in-system test. - Developing and maintaining DFT STA constraints, timing exceptions, and signoff methodologies throughout the design lifecycle. - Ensuring the robust timing of DFT infrastructure, encompassing test clocks, OCCs, clock muxing, and clock-gating architecture. - Analyzing and resolving DFT timing issues in complex multi-clock and low-power designs using advanced STA techniques. - Developing automation and AI-assisted workflows to enhance DFT timing analysis, signoff efficiency, and overall productivity. - Supporting post-silicon debug by correlating timing analysis with silicon test results and leading root-cause resolution efforts. - Providing technical leadership and fostering collaboration across Architecture, Design, Verification, Physical Design, CAD, Manufacturing, and Post-Silicon teams to ensure the delivery of high-quality silicon.

We are looking for an experienced Silicon Design for Test (DFT) Engineer with a Bachelor's, Master's, or Ph.D. in Electrical Engineering or Computer Engineering, coupled with over 5 years of combined experience in DFT and STA.

A strong understanding of industry-standard practices in Design for Test, including ATPG, JTAG, and Memory BIST, along with knowledge of the trade-offs between test quality and test time, is essential.

Preferred qualifications include experience in developing Scan architecture and micro-architecture specifications for large SOCs, alongside scan insertion techniques for IP blocks like PLLs, IOs, and power circuits. Expertise in Scan ATPG, Stuck-At, At-Speed insertion, boundary coverage, compression, and retargeting flows using EDA tools such as Siemens Tessent or Synopsys TestMax is highly desirable.

Furthermore, proficiency in constraint development and timing closure for DFT modes, including in-depth analysis of timing paths using Primetime Static Timing Analysis (STA), CDC, and RDC, is crucial. The ability to automate SDC generation and leverage EDA tool-generated SDCs for local consumption is also valued.

Experience with tools like Genus or Fusion Compiler at lower process nodes, coupled with strong scripting skills in Tcl and Perl, and the application of AI to enhance work efficiency, will be advantageous. We seek proactive, self-motivated individuals eager to learn, contribute within a team, and demonstrate commitment and accountability. A confident problem-solving approach that thrives under pressure to find novel, creative solutions is key.