Join a pioneering team developing custom silicon solutions that power Google Cloud's direct-to-consumer products. You will be instrumental in shaping the next generation of hardware, delivering exceptional performance, efficiency, and integration for products used by millions globally. Your expertise will directly influence the advanced computing infrastructure that underpins Google's services.

This role offers a unique opportunity to work on systems at the core of the world's largest computing infrastructure. You will contribute to designs that span from fundamental circuit levels to comprehensive system architectures, following them through high-volume manufacturing. The impact of your work can be profound, shaping the very machinery that drives our data centers and enhances the experience for countless Google users.

Develop and define the overall DFT strategy and architecture, including approaches for hierarchical DFT, high-speed I/Os, and analog circuits.

Drive the die-level DFT validation strategy, ensuring rigorous Test Design Rule Checks (TDRC) and implementing necessary design modifications to meet stringent test quality standards.

Implement critical DFT logic, encompassing boundary scan, scan chains, advanced compression techniques, Logic BIST, TAP controllers, clock management blocks, and other essential DFT IP.

Create comprehensive documentation for the DFT architecture, test sequences, and boot-up procedures relevant to test pins.

Generate and deliver production and debug patterns for the post-silicon engineering team, and provide crucial diagnostic support for silicon bring-up and debugging.

A Bachelor's degree in Electrical Engineering or a related technical field, or equivalent practical experience, is required.

Possess at least 8 years of hands-on experience in implementing and validating cutting-edge DFT technologies.

Demonstrate extensive experience across multiple projects in DFT design, verification, specification, architecture, and insertion.

Exhibit a strong track record with DFT techniques and tools, including proficiency in ASIC DFT synthesis, simulation, and the entire verification flow.

Proven ability to lead DFT activities effectively throughout the complete ASIC development lifecycle.