Join a forward-thinking team dedicated to advancing custom silicon solutions that power Google's innovative direct-to-consumer products. You will play a key role in shaping the future of hardware, contributing to exceptional performance, efficiency, and seamless integration in products used by millions globally.

The AI and Infrastructure team is at the forefront of innovation, delivering AI and Infrastructure at an unprecedented scale, efficiency, and reliability. Our solutions empower Google's internal teams, Google Cloud customers, and billions of users worldwide, driving breakthroughs in AI models and computing power.

Plan and execute comprehensive verification strategies for digital design blocks, ensuring deep understanding of specifications and collaborating with design engineers on critical scenarios.

Develop and refine constrained-random verification environments using SystemVerilog and UVM, employing SystemVerilog Assertions and leading formal verification tools.

Define and implement all types of coverage measures for stimuli and corner cases.

Collaborate with design engineers to debug tests and deliver functionally correct design blocks.

Achieve coverage closure to identify verification gaps and confirm readiness for tape-out.

A Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.

Minimum of 8 years of experience in RTL-level verification of digital logic using SystemVerilog or Specman/E for FPGAs or ASICs.

Proven experience in verification and debug of IPs, subsystems, or SoCs within the networking domain, including packet processing, bandwidth management, and congestion control.

Demonstrated experience verifying digital systems with standard IP components and interconnects, such as microprocessor cores and hierarchical memory subsystems.

Preferred qualifications include a Master's degree or PhD in a relevant field with a focus on computer architecture, alongside experience in performance verification, ASIC interfaces, memory system architecture, and AI/ML accelerators or vector processing units.