Join a pioneering team shaping the future of Google's direct-to-consumer products with custom silicon solutions. Your expertise will drive innovation, delivering unparalleled performance and efficiency for next-generation hardware experiences. This role is instrumental in advancing AI and Infrastructure capabilities at Google, impacting users, developers, and Google Cloud customers worldwide.

Our team is at the forefront of Google's technological advancements. We provide the computing power for cutting-edge AI models and global services, while developing essential platforms for developers. Our work spans from software to hardware, including TPUs, Vertex AI, Google Global Networking, and Data Center operations, contributing to world-leading hyperscale computing.

Plan and execute comprehensive verification strategies for digital design blocks by thoroughly understanding specifications and collaborating with design engineers on critical verification scenarios.

Develop and enhance constrained-random verification environments using SystemVerilog and UVM. Employ SystemVerilog Assertions and industry-leading formal tools for design verification.

Define and implement all necessary coverage measures to capture stimulus and corner-case scenarios. Identify and address verification holes to ensure functional correctness and track progress towards tape-out.

Collaborate closely with design engineers to debug tests and deliver functionally sound design blocks. Ensure complete coverage by meticulously closing all measures.

A Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience, is required.

Possess a minimum of 8 years of experience in verification, specifically in verifying digital logic at the RTL level using SystemVerilog or Specman/E for FPGAs or ASICs.

Demonstrate experience in the verification and debug of IPs, subsystems, or SoCs within the networking domain, including areas like packet processing, bandwidth management, and congestion control.

Proven experience in verifying digital systems utilizing standard IP components and interconnects, such as microprocessor cores and hierarchical memory subsystems.