Join a pioneering team at Google Cloud, driving innovation in custom silicon solutions that power Google's direct-to-consumer products. Your contributions will shape the next generation of hardware, delivering exceptional performance, efficiency, and integration for products used by millions globally. This role is key to advancing AI/ML capabilities on Tensor Processing Units (TPUs).

The AI and Infrastructure team is at the forefront of technological advancement, providing AI and Infrastructure solutions at an unprecedented scale and efficiency. We empower Google's customers, including internal teams, Google Cloud users, and billions of global users, with cutting-edge capabilities and insights. Our work fuels Google's groundbreaking AI models and provides the essential platforms for developers worldwide.

As a Senior Silicon Design Verification Engineer, you will be responsible for the entire verification life-cycle, from planning and test execution to coverage closure, with a sharp focus on meeting AI/ML performance and accuracy objectives. You will develop advanced constrained-random verification environments to uncover complex bugs and ensure the robustness of AI/ML workloads on TPU hardware.

Key duties include: - Planning verification for digital design blocks by thoroughly understanding specifications and collaborating with design engineers. - Creating and improving constrained-random verification environments using SystemVerilog and UVM. - Employing SystemVerilog Assertions and leading formal tools for design verification. - Defining and implementing various coverage measures for stimulus and corner-cases. - Debugging tests alongside design engineers to ensure functionally correct design blocks. - Achieving coverage closure to identify verification gaps and confirm readiness for tape-out.

A Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related discipline, or equivalent practical experience, is required. You should possess at least 8 years of experience in RTL-level verification of digital logic, utilizing SystemVerilog or Specman/E for FPGAs or ASICs.

Experience in verification and debugging of IPs, subsystems, or SoCs within the networking domain is essential, covering areas like packet processing, bandwidth management, and congestion control. Familiarity with verifying digital systems using standard IP components and interconnects, such as microprocessor cores and hierarchical memory subsystems, is also necessary.

Preferred qualifications include a Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science with a focus on computer architecture. Experience with industry-standard simulators, revision control, and regression systems is beneficial. Expertise in AI/ML accelerators or vector processing units, along with a comprehensive understanding of the full verification life cycle, is highly desirable. Excellent problem-solving and communication skills are expected.