Join a forward-thinking team dedicated to developing advanced custom silicon solutions that drive Google's consumer products. You will be instrumental in innovating hardware experiences, delivering exceptional performance, efficiency, and integration for products used by millions globally.

The AI and Infrastructure team is at the forefront of innovation, empowering Google users worldwide with cutting-edge AI and infrastructure at an unprecedented scale. This includes supporting Google's internal teams, Google Cloud customers, and billions of end-users.

We are the driving force behind Google's technological leaps, enabling the creation of advanced AI models, providing massive computing power for global services, and building the foundational platforms for developers. Our work spans from software to hardware, influencing the future of hyperscale computing with projects like TPUs, Vertex AI, Google Global Networking, and data center operations.

Your role will involve meticulous planning for digital design block verification, driven by a deep understanding of specification documents and close collaboration with design engineers to pinpoint critical verification scenarios.

You will architect and refine constrained-random verification environments using SystemVerilog and UVM. Designs will be rigorously verified using SystemVerilog Assertions and leading formal verification tools.

Key tasks include identifying and implementing all necessary coverage metrics for stimuli and corner-cases. You will collaborate closely with design engineers to debug tests and ensure functionally sound design blocks are delivered.

Your efforts will focus on closing coverage metrics to expose verification gaps and demonstrate readiness for tape-out.

A Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related discipline, or equivalent practical experience, is required. You should possess 8 years of hands-on experience in creating and utilizing verification components and environments within standard verification methodologies.

Proven experience in verifying complex digital systems, including standard IP components and interconnects like microprocessor cores and hierarchical memory subsystems, is essential. Familiarity with the entire verification lifecycle and various verification techniques is expected.

Experience with performance verification for ASICs and their components is also a key requirement. Demonstrating involvement in multiple SoC/IP projects across 3 or more product cycles is necessary.

Preferred qualifications include a Master's or PhD in Electrical Engineering, Computer Engineering, or Computer Science, with a specialization in computer architecture. Experience with industry-standard simulators, revision control systems, and regression systems is advantageous, as is experience in AI/ML accelerators or vector processing units. Exceptional problem-solving and communication abilities are highly valued.