Join a forward-thinking team dedicated to crafting advanced silicon solutions that power Google's consumer products. You will be instrumental in driving innovation for products used by millions globally.

Your expertise will be crucial in shaping the next generation of hardware, ensuring exceptional performance, efficiency, and seamless integration. The AI and Infrastructure team is at the forefront of technological advancement, enabling Google's customers with cutting-edge capabilities and insights through AI and Infrastructure at an unprecedented scale, efficiency, reliability, and velocity.

Our impact extends across Google employees, Google Cloud customers, and billions of users worldwide. We are the engine behind Google's significant innovations, supporting the development of advanced AI models, delivering massive computing power to global services, and providing the foundational platforms for future developer endeavors. From software to hardware, our teams are defining the future of world-class hyperscale computing.

You will be responsible for meticulously planning the verification of digital design blocks, achieving a deep understanding of design specifications. This involves close collaboration with design engineers to pinpoint critical verification scenarios.

Develop and refine constrained-random verification environments utilizing SystemVerilog and Universal Verification Methodology. Employ SystemVerilog Assertions and leading formal tools for design verification. Identify and implement all forms of coverage measures for stimulus and corner-case scenarios.

Collaborate with design engineers to debug tests and ensure the delivery of functionally sound design blocks. Achieve coverage measure closure to uncover verification gaps and demonstrate readiness for tape-out.

A Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience, is required. Candidates must possess 8 years of experience in developing and employing verification components and environments within standard verification methodologies.

Proven experience in verifying digital systems using standard IP components and interconnects, such as microprocessor cores and hierarchical memory subsystems. Familiarity with comprehensive verification techniques and the entire verification lifecycle is essential. Experience in performance verification of ASICs and their components is expected.

Demonstrated experience across multiple SoC/IP projects and product cycles, ideally involving three or more distinct products. Preferred qualifications include a Master's degree or PhD in a relevant engineering or computer science field with a focus on computer architecture, alongside experience with industry-standard simulators, revision control systems, and regression systems.