Shape the future of AI/ML hardware acceleration by driving cutting-edge TPU technology that powers Google's most demanding applications. Join a team pushing boundaries in custom silicon solutions for Google's TPUs and contributing to products used by millions worldwide.

Leverage your design and verification expertise to ensure the integrity of complex digital designs, focusing specifically on TPU architecture and its integration within AI/ML-driven systems. Collaborate with Architecture, Verification, Power and Performance, and Physical Design teams to deliver high-quality designs for next-generation accelerators.

The AI and Infrastructure team redefines possibilities by delivering AI and Infrastructure at unparalleled scale, efficiency, and velocity. We empower Google customers, Googlers, and billions of users with breakthrough capabilities. We are the driving force behind Google's groundbreaking innovations, enabling cutting-edge AI models, unparalleled computing power, and essential platforms for developers.

Participate in the design, implementation, and integration of chassis, subsystems, and SoCs, including technology migration of standard, foundational, and third-party intellectual property (3PIPs).

Perform RTL coding for subsystems/SoC integration, function/performance simulation debugging, and execute quality checks like Lint, CDC, RDC, and VCLP.

Engage in design debugging and code reviews in collaboration with other IP Design Verification (DV) teams and physical design teams.

Coordinate effectively with various IP teams to meet stringent schedule and quality requirements.

A Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience is required.

Requires 8 years of experience in digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog.

Possess 8 years of experience in the design, implementation, and integration of chassis, subsystems, and SoCs. Experience with logic synthesis for RTL code, performance, and power is essential, along with expertise in low-power design.

Preferred qualifications include a Master's degree or PhD with 10 years of relevant industry experience, along with expertise in owning medium complex SoC integration and QC. Experience with scripting languages like Python or Perl, tape-outs, and bring-up support is beneficial. A strong understanding of arithmetic units, bus architectures, processor design, accelerators, or memory hierarchies, and proficiency in Verilog or SystemVerilog are also advantageous.