Shape the future of AI/ML hardware acceleration by driving cutting-edge TPU technology. Join a team dedicated to developing custom silicon solutions for Google's demanding AI/ML applications. Contribute to innovation and leverage your design and verification expertise within AI/ML-driven systems, focusing on TPU architecture and integration.

This role involves developing Application-Specific Integrated Circuits (ASICs) for machine learning computation in data centers. You'll collaborate with various teams to deliver high-quality designs for next-generation accelerators, focusing on micro-architecture innovation and balancing performance with power.

The AI and Infrastructure team is redefining possibilities, empowering Google customers with scalable, efficient, and reliable AI and Infrastructure. We drive groundbreaking innovations, deliver computing power to global services, and provide platforms for developers. Our work spans TPUs, Vertex AI, Global Networking, and data center operations, shaping the future of hyperscale computing.

Engage in the design, implementation, and integration of chassis, subsystems, and SoCs. This includes technology migration for standard, foundational, and third-party intellectual property (3PIPs).

Perform RTL coding for Subsystem/SoC integration, debug functional/performance simulations, and conduct Lint/CDC/FV/UPF checks. Execute quality check flows such as Lint, CDC, RDC, and VCLP.

Participate in design debugging and code reviews in close coordination with other IP Design Verification (DV) and physical design teams. Collaborate with various IP teams to ensure schedule and quality objectives are met.

A Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience is required.

Possess 8 years of experience in digital logic design principles, RTL design concepts, and languages like Verilog or SystemVerilog. An additional 10 years of relevant industry experience is preferred for candidates with a Master's or PhD.

Demonstrate 8 years of experience in the design, implementation, and integration of chassis, subsystems, and SoCs. Experience with logic synthesis for RTL code, performance, and power optimization, as well as low-power design principles, is essential.

Preferred qualifications include experience in owning medium-complex SoC integration and quality control, proficiency in scripting languages such as Python or Perl, and familiarity with tape-outs and bring-up support. Knowledge of arithmetic units, bus architectures, processor design, accelerators, or memory hierarchies is also beneficial.