Shape the future of AI/ML hardware acceleration by driving cutting-edge TPU (Tensor Processing Unit) technology. This role offers the chance to develop custom silicon solutions powering Google's most demanding AI/ML applications and contribute to innovation behind widely used products. Leverage your design and verification expertise to ensure complex digital designs, with a focus on TPU architecture and its integration within AI/ML-driven systems, meet stringent requirements.

Join a dynamic team focused on developing Application-Specific Integrated Circuits (ASICs) to accelerate machine learning computation in data centers. Collaborate closely with Architecture, Verification, Power and Performance, and Physical Design teams to deliver high-quality designs for next-generation accelerators. You will tackle technical challenges through micro-architecture innovation and expertly evaluate design trade-offs between performance and power.

The AI and Infrastructure team is redefining possibilities, empowering Google customers with breakthrough capabilities and insights through AI and Infrastructure at unparalleled scale, efficiency, and velocity. Our reach extends to Googlers, Google Cloud customers, and billions of users globally. We are the driving force behind Google's groundbreaking innovations, enabling the development of advanced AI models, delivering immense computing power, and providing essential platforms for developers to build the future.

Engage in the design, implementation, and integration of chassis, subsystems, and SoCs, including technology migration for standard, foundational, and third-party intellectual property (3PIPs).

Perform RTL coding for subsystems/SoC integration, function/performance simulation debugging, Lint/CDC/FV/UPF checks, and quality assurance flows like Lint, CDC, RDC, and VCLP.

Participate in design debugging and code reviews in close coordination with other IP Design Verification (DV) teams and physical design teams.

Coordinate with various IP teams to ensure timely delivery and adherence to quality standards.

A Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience is essential.

Possess at least 8 years of hands-on experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog.

Demonstrate 8 years of experience in the design, implementation, and integration of chassis, subsystems, and SoCs.

Significant experience with logic synthesis for RTL code, focusing on performance and power optimization, along with expertise in low-power design techniques.

Preferred qualifications include a Master's degree or PhD in Electrical Engineering or Computer Science, or equivalent practical experience with 10 years of relevant industry expertise. Experience in owning medium complex SoC integration and quality control, proficiency in scripting languages like Python or Perl, and familiarity with tape outs and bring-up support are highly valued. Knowledge of arithmetic units, bus architectures, processor design, accelerators, or memory hierarchies, alongside a strong understanding of Verilog or SystemVerilog, would be advantageous.