NVIDIA is at the forefront of building advanced accelerated computing systems, requiring seamless integration of platform manageability, secure firmware, and high-performance networking. This role is pivotal in defining and implementing OpenBMC-based management for complex systems that encompass host CPUs, BMCs, and coordinated top-of-rack Ethernet switching.

The position extends the traditional server management controller into a robust secure management authority. It ensures system and Ethernet switch management are handled effectively while maintaining a clear separation between the BMC management plane and the switch data plane. Join us to shape the future of OpenBMC networking architecture, platform firmware, system management, and enterprise network infrastructure.

Architect and deploy OpenBMC support for platforms integrating BMCs with host system functions and coordinated Top-of-Rack (ToR) Ethernet switch subsystems.

Define the comprehensive switch-management architecture, encompassing OpenBMC D-Bus services, bmcweb/Redfish APIs, configuration management, eventing, telemetry, security protocols, and backend switch control interfaces.

Develop intricate OpenBMC object models and services for managing switch inventory, ASICs, front-panel and internal ports, optics, retimers, VLANs, link aggregation groups (LAGs), Forwarding Database (FDB) entries, sensor data, and overall system health.

Implement Layer 2 networking functionalities, including port administration, speed and Forward Error Correction (FEC) configuration, auto-negotiation, breakout capabilities, VLAN management, access/trunk modes, MAC learning, FDB operations, flooding controls, link aggregation, and loop prevention mechanisms.

Construct backend abstraction layers to integrate with diverse Linux networking components such as switchdev/netlink, SAI/SONiC/SWSS-style frameworks, DENT-style networking solutions, or specific vendor switch ASIC SDKs.

Collaborate closely with cross-functional teams including hardware, ASIC, security, firmware, quality assurance, manufacturing, and cloud infrastructure networking to influence board design, schematics, manageability interfaces, and production testing strategies.

Produce and meticulously review design specifications, API documentation, source code, unit tests, hardware-in-the-loop tests, integration test plans, and quality assurance plans essential for productizing the defined architecture.

A Bachelor's degree or higher, or equivalent practical experience, in Computer Science, Electrical and Electronics Engineering, or a closely related field, combined with over 12 years of pertinent professional experience.

Proven expertise in OpenBMC firmware development within x86 or ARM-based server environments. This includes extensive experience with Yocto, systemd, D-Bus, phosphor services, bmcweb, Redfish, firmware update processes, device monitoring, and platform security implementations.

Demonstrated hands-on experience with Ethernet switch architecture and Layer 2 features such as VLANs, trunks, access ports, Link Aggregation Control Protocol (LAG/LACP), Spanning Tree Protocol (STP/RSTP), Link Layer Discovery Protocol (LLDP), FDB/MAC learning, storm control, Access Control Lists (ACLs), Quality of Service (QoS), PHY management, and transceiver diagnostics.

Substantial experience in system management software for rack or blade server platforms, including familiarity with IPMI, KCS, Redfish, PLDM, MCTP, SPDM, secure firmware updates, attestation mechanisms, and robust BMC-host communication protocols.

Exceptional programming and debugging proficiency in C/C++ and Python, coupled with familiarity in Bash, Go, or Rust. The ability to develop reliable Linux user-space services and critically review low-level system code is essential.

Outstanding written and verbal communication skills, a strong sense of ownership, high-level engineering judgment, and a genuine passion for tackling complex, multi-disciplinary problems.