Join NVIDIA's elite team of design engineers, contributing to groundbreaking GPUs and SOCs. This role offers a unique opportunity to significantly impact product lines spanning consumer graphics, autonomous vehicles, and the rapidly evolving field of artificial intelligence. Become part of a global collective dedicated to pushing the boundaries of what's possible and shaping the future of computing.

Take ownership of full-chip physical verification, guiding designs from block-level assembly through final tapeout on cutting-edge process nodes like TSMC A16 and TSMC 3nm. Ensure signoff for DRC, LVS, and antenna checks across all design levels, driving convergence to a clean tapeout database. Advance the frontiers of 3D die stacking and heterogeneous integration by verifying die-to-die interfaces and unifying dies from diverse process nodes. Spearhead innovation in Angstrom-class technology, enabling signoff for advancements such as Super Power Rail backside power delivery and nanosheet GAA transistors. Revolutionize signoff processes using AI, developing ML and LLM-powered automation for root-cause analysis and flow optimization. Collaborate closely with methodology and CAD/technology teams to implement correct-by-construction flows that identify issues early and minimize signoff iterations. Engage in cross-functional partnerships with P&R, Timing, IR, and Library teams to ensure timely design closure.

A Bachelor's or Master's degree in Engineering (BE/B.Tech/M.Tech) or an equivalent qualification is required, coupled with over 5 years of experience in Physical Design Verification, full-chip integration, and tapeouts on the latest technology nodes. A robust understanding of Physical Implementation and VLSI design principles is essential. Proficiency with signoff tools such as Calibre, ICV, EDI, and FC is a must. A solid grasp of RTL2GDSII concepts, including synthesis, place & route, CTS, timing convergence, and layout closure, is also necessary. Excellent problem-solving abilities are highly valued.