Join NVIDIA, a company that has continuously reinvented itself, sparking the growth of PC gaming, redefining computer graphics, and revolutionizing parallel computing. We are a learning machine, constantly adapting to address complex, world-impacting challenges. Immerse yourself in a diverse and supportive environment where innovation thrives. We are seeking passionate and creative design engineers to contribute to industry-leading GPUs and SOCs, impacting product lines from consumer graphics to AI and self-driving cars. Be part of a global team pushing the frontiers of computing and defining its future.

Engage with the physical design methodology team, contributing to floor plans, abstract view generation, RC extraction, PNR, STA, EMIR DROP, DRCs, and schematic-to-layout verification. Collaborate closely with the design team to overcome challenges and assist colleagues with debugging. Continuously seek improvements in the RTL2GDS flow to enhance power, performance, and area (PPA). Troubleshoot complex design issues proactively. Develop scripts (TCL/Python) to empower design teams and achieve chip goals. Construct efficient flows using industry-standard EDA tools for design implementation and PPA improvement, supporting chip design teams across various tapeouts and technology nodes.

A Bachelor's or Master's degree in Engineering (BE/B.Tech/M.Tech) or equivalent practical experience is required. A minimum of 3 years of experience in Physical Design, with a preference for methodology/flow expertise. Strong command of the RTL2GDSII flow and design implementation in leading process technologies, including synthesis, place & route, CTS, timing convergence, and layout closure. Expertise in high-frequency design methodologies and hands-on experience with block-level and full-chip floor-planning and physical verification. Proficiency with EDA tools such as ICC2/Innovus and Primetime/Tempus/Seahawk for RTL2GDSII implementation. Solid understanding of standard place and route flows (ICC2/Synopsys and Innovus/Cadence preferred), timing constraints, STA, IR drop analysis, and ECO timing closure. Strong algorithmic thinking and automation skills, with proficiency in PERL, TCL, and tool-specific scripting for Place & Route tools; Python skills are also beneficial. Ability to manage multiple tasks effectively and adapt to a global work environment, coupled with excellent communication, analytical, and problem-solving skills. A proactive attitude towards learning new techniques and driving innovation across teams and workflows is essential.