Join NVIDIA, a leader in GPU innovation, and contribute to cutting-edge memory mask design. This role involves working on challenging high-speed digital memory circuit designs, pushing the boundaries of technology in advanced CMOS process nodes.

NVIDIA is a dynamic environment that fosters continuous learning and adaptation. We are looking for individuals driven by solving complex problems and making a significant impact on the world. Be part of a supportive and diverse team where your contributions are valued and amplified.

Implement IC layouts for innovative, high-speed CMOS circuits across advanced process nodes (3nm, 5nm, 7nm, and below).

Lead the architecture and layout design of critical memory subsystems, including control logic, sense amplifiers, I/O blocks, bit-cell arrays, and decoders.

Oversee custom layout and verification of complex memory cells, establishing standards for compiler-driven design flows.

Manage and optimize all physical verification activities, ensuring comprehensive tape-out checks.

Drive the resolution of physical design issues in compiler-generated layouts, mentoring junior engineers.

Provide expert guidance on IR drop and EM mitigation, developing robust memory layout methodologies.

Requires a B.E/B.Tech or M.Tech in Electronics, or equivalent experience, with at least 6 years of proven experience in memory layout within advanced CMOS processes.

Proficiency with industry-standard EDA tools, particularly Cadence, is essential.

Experience with high-performance memory layouts of various types is necessary.

Solid understanding of layout fundamentals, including bitcells, decoders, LIO, matching devices, symmetrical layout, and signal shielding.

Familiarity with floor planning, block-level routing, and macro-level assembly.

Detailed knowledge of top-level verification, EM/IR checks, and layout-dependent effects (LOD, dummification, fills).