Join NVIDIA, a leader in GPU and SOC innovation, and contribute to groundbreaking solutions across diverse sectors. We are seeking a dedicated Senior Mask Design Engineer to drive advancements in power, performance, and efficiency.

This role offers the opportunity to collaborate with a leading package technical lead and various design teams. You will be instrumental in designing and developing intricate silicon interposer layouts for NVIDIA's cutting-edge products. Your responsibilities will extend to strategic planning for schedules, cost management, and resolving manufacturing and electrical design challenges.

Engage cross-functionally with the Package Technical Lead (PTL), I/O signal integrity, and technology engineers to deliver product package solutions within demanding timelines.

Execute physical layout for silicon interposers utilizing Cadence tools.

Conduct feasibility studies to assess package design goals related to size, cost, and system performance.

Participate in layout floorplan analysis and perform custom layout, verifying against design rules and netlists.

Propose layout design trade-offs to the PTL for review and implementation.

A Bachelor of Science in Electrical Engineering or equivalent experience is required.

Possess a minimum of 5 years of proven experience in Mask and Layout Design.

Demonstrate a deep understanding of layout concepts within submicron CMOS technologies.

Exhibit mastery of Cadence layout tools, with a focus on Virtuoso.

Experience with verification tools such as Calibre, ICV, or Thunder is essential.

Proficiency in scripting languages like Perl, Python, and SKILL is necessary.

Strong knowledge of DRC and LVS checking flows, with the ability to customize decks.

Exceptional teamwork, interpersonal skills, passion, and positive energy are crucial for success in this role.