Join a forward-thinking team at Google Cloud, dedicated to developing custom silicon solutions that will power Google's future direct-to-consumer products. You will play a pivotal role in shaping innovative hardware experiences, driving unparalleled performance, efficiency, and integration for products used by millions globally.

This is an opportunity to contribute to the forefront of AI and Infrastructure, empowering Google customers with groundbreaking capabilities and insights. You'll help deliver AI and Infrastructure at an unprecedented scale, ensuring efficiency, reliability, and velocity for both internal Googlers and external Google Cloud customers.

As a Senior IP/Sub System Design Verification Engineer, you will lead the entire verification lifecycle, from initial planning and test execution through to coverage closure. A key focus will be meeting stringent AI/ML performance and accuracy targets. You will develop sophisticated constrained-random verification environments to uncover challenging corner-case bugs and guarantee the robustness of AI/ML workloads on Tensor Processing Unit (TPU) hardware. Close collaboration with design and verification engineers on active projects will be essential for successful verification tasks.

The role requires a Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related discipline, alongside 8 years of professional experience in verification. Expertise in verifying digital logic at the Register-Transfer Level (RTL) using SystemVerilog or Specman/E for FPGAs or ASICs is crucial. Experience with standard IP components and interconnects, such as microprocessor cores and hierarchical memory subsystems, is necessary. Additionally, a background in the verification and debug of IP/subsystems within the networking domain, including packet processing and bandwidth management, is required. A Master's degree or PhD in a relevant engineering or computer science field, with a focus on computer architecture, is preferred.