Join NVIDIA's Silicon Co-Design Group as a Senior High-Speed IO Validation Engineer. This pivotal role focuses on the characterization and qualification of critical high-speed interfaces such as PCIe, NVLink, UCIe, USB, UFS, and Ethernet on cutting-edge GPUs, SoCs, and CPUs. Your expertise will directly impact products serving datacenter, AI, and client markets, ensuring robust performance from initial silicon power-on through to high-volume production.

You will be instrumental in bridging the gap between silicon design and real-world application, meticulously testing and validating every aspect of high-speed interconnects.

Take ownership of the end-to-end characterization and validation of high-speed IO interfaces, covering silicon, package, and board levels for NVIDIA's advanced GPUs, CPUs, and SoCs. Develop and execute comprehensive validation test plans, including bring-up, corner qualification, stress testing, and structured Design of Experiments (DOE) across various environmental and firmware conditions.

Drive power characterization and optimization, analyze trade-offs, and provide crucial feedback to design and firmware teams. Conduct systematic root-cause analysis for complex IO bugs, collaborating across silicon, package, board, firmware, and driver teams. Evaluate manufacturing and yield implications of IO margin distributions, contributing to binning and design improvements. Enhance validation methodologies, automation frameworks, and margin-tracking infrastructure to boost efficiency and coverage.

A Bachelor of Science (BS) or Master of Science (MS) in Electrical or Computer Engineering, or a related field, coupled with over 6 years of experience in post-silicon HSIO validation or characterization, is essential. A deep understanding of high-speed serial link protocols (PCIe Gen5+, NVLink, UCIe, CXL) and SERDES architecture, including equalization, link training, and electrical characterization, is required.

Strong fundamentals in Signal Integrity (SI) and Power Integrity (PI), encompassing S-parameters, eye diagrams, channel margin, and PDN noise, are crucial. Hands-on experience with lab instrumentation (DSOs, BERTs, VNAs, protocol/logic analyzers, TDR) and Python-based test automation is necessary. Experience with DOE/shmoo/margin-trending techniques and a proven ability to drive cross-functional debug across hardware, firmware, and software teams are highly valued.