Join NVIDIA's newly formed team in Bangalore as a Senior GPU Floorplan Design Engineer, shaping the future of leading-edge GPUs. This pivotal role integrates architecture, RTL, performance analysis, and physical design, with a focus on forward planning, feasibility, and physical trade-offs. Contribute to next-generation GPU design and development, impacting diverse product lines from consumer graphics and self-driving cars to artificial intelligence. Be part of a global team pushing technological boundaries and defining future computing platforms.

NVIDIA is renowned as a highly sought-after tech employer. Our innovations are driving breakthroughs in Artificial Intelligence, Autonomous Driving, High-Performance Computing, and Visualization. We employ some of the world's most forward-thinking and dedicated individuals. If you possess creativity, autonomy, and a passion for designing the fastest, most power-efficient chips, we encourage you to apply.

Collaborate closely with architects, design leads, physical design leads, and package leads to develop and optimize chip floorplans during the early stages of development.

Lead the area review process, partnering with the ASIC design team to pinpoint opportunities for improving area, interconnectivity, and floorplan design.

Address timing and routing congestion challenges by influencing early design and physical implementation decisions in conjunction with the physical and ASIC design teams.

Develop new tools and enhance existing infrastructure to optimize chip area and accelerate execution speed.

Hold a B.Tech. or M.Tech. degree and possess over 5 years of experience in floorplan design, SOC planning, ASIC physical design, or related engineering fields.

Demonstrate a deep hardware engineering background with expertise in VLSI and/or Computer Architecture.

Showcase hands-on experience in chip-level or subsystem-level floorplanning and physical planning.

Possess a strong understanding of timing, congestion, power distribution, and physical design constraints.

Have experience with hardware description languages such as Verilog or System Verilog.

Familiarity with CAD tools, physical design methodologies (flow and tool development), chip floorplan design, power/clock distribution, packaging, place and route (P&R), and timing closure is essential.

Exhibit excellent communication and interpersonal skills, with a proven ability and desire to collaborate effectively within a team environment.

Proficiency in programming languages including Python, Perl, and C/C++ is required.