Join NVIDIA, a leader in reinvention and innovation, shaping the future of computing. We are a "learning machine" constantly adapting to solve challenging problems that matter. As part of our diverse and supportive team, you'll amplify human creativity and intelligence. The IODFX Engineering team is at the forefront of innovation, developing groundbreaking solutions for IO and interconnect testing for complex semiconductor chips, from consumer graphics to AI and self-driving cars.

Immerse yourself in an inclusive environment where your best work is inspired. You'll contribute to high-speed IO testing, essential for our product lines. Our team crafts creative solutions, driving advancements in a field that demands sophisticated speeds and robust manufacturing testability. Come make a lasting impact on the world with us.

Spearhead POR to Post Silicon Testing of DFX features for high-speed IOs, crafting crucial test features for manufacturing. Architect, design, and validate these features with scalable test plans at unit and SOC/Full Chip levels using UVM and NVIDIA internal tools.

Perform Pre-Silicon simulation and debug, ensuring robust test functionality with industry-standard tools. Sign off on test coverage using established metrics for diverse products.

Drive automation, flow development and improvement, coverage metric analysis, test execution, and bug identification. Productize IO test solutions, solving complex mixed-signal test problems with scalable, cross-platform solutions.

Collaborate with IP teams on IOBIST test-logic design, and with Mixed Signal Circuit design teams on analog components. Partner with other DFX teams, coordinate with Post Silicon Test and Production Engineering for efficient, quality test productization.

A Bachelor's or Master's degree in Electrical Engineering (EE), Electronics and Communication Engineering (ECE), or equivalent experience is required.

Possess strong analytical and problem-solving skills, coupled with a solid understanding of logic design, architecture, and verification methodologies.

Demonstrate robust coding proficiency in industry-standard scripting languages. Experience in DFT and/or industry-standard verification flows such as constrained random testing, UVM, coverage metrics, profiling tools, or X Prop is highly beneficial, with a preference for candidates possessing 3+ years of relevant experience.

Exhibit outstanding written and oral communication skills, driven by a genuine curiosity to learn and grow within a dynamic engineering environment.