Join Google Cloud as a Senior DFT Design/Micro-architect Engineer and shape the future of AI/ML hardware acceleration. You will be instrumental in driving cutting-edge TPU (Tensor Processing Unit) technology, powering Google's most demanding AI/ML applications. This role offers the unique opportunity to develop custom silicon solutions, pushing boundaries in a team dedicated to innovation. Leverage your design and verification expertise to ensure the robustness of complex digital designs, with a specialized focus on TPU architecture and its seamless integration within AI/ML-driven systems.

Our computational challenges are immense, requiring us to create bespoke hardware solutions. Your contributions will be vital in designing and building the hardware, software, and networking technologies that underpin all of Google's services, impacting millions of users worldwide. This position is key to defining, designing, and analyzing DFT implementations and flows that support the core systems of our powerful computing infrastructure.

Define and drive the DFT strategy and architecture, encompassing areas like hierarchical DFT, high-speed I/Os, and analog DFT.

Develop and execute a comprehensive die-level DFT validation strategy, ensuring all Test Design Rule Checks (TDRC) are met and Design changes are implemented to achieve superior test quality.

Integrate essential DFT logic, including boundary scan, scan chains, DFT Compression, Logic BIST, TAP controllers, Clock Control blocks, and other critical DFT IP.

Create detailed documentation for the DFT architecture, test sequences, and boot-up sequences related to test pins.

Generate and deliver production and debug patterns to the Post Silicon engineering team, providing crucial support for post-silicon validation and diagnosis.

A Bachelor's degree in Electrical Engineering or a related field, or equivalent practical experience, is essential.

Minimum of 8 years of hands-on experience in the implementation and validation of Design for Testability (DFT) technologies.

Proven track record with multiple projects in DFT design and verification, encompassing DFT specification, definition, architecture, and insertion.

Proficiency with DFT techniques and tools, including ASIC DFT synthesis, simulation, and the complete verification flow.

Demonstrated experience in leading DFT activities throughout the entire ASIC development lifecycle.