Shape the future of AI/ML hardware acceleration by driving cutting-edge TPU technology for Google's demanding applications. Join a pioneering team developing custom silicon solutions that power Google's future TPUs. Your expertise in design and verification will be crucial in validating complex digital designs, with a particular focus on TPU architecture and its integration into AI/ML systems.

We tackle computational challenges so immense and unique that they necessitate in-house hardware development. Our team is responsible for the hardware, software, and networking technologies powering all of Google's services.

As a DFT micro architect/design Engineer, you will define, design, and analyze DFT implementations and flows that support the core systems of the world's largest and most powerful computing infrastructure. You'll see systems through from intricate circuit design to large-scale system development and high-volume manufacturing. Your contributions will directly impact the machinery in our advanced data centers, influencing millions of Google users. The AI and Infrastructure team is at the forefront of innovation, enabling breakthrough AI capabilities and insights through unparalleled scale, efficiency, reliability, and velocity. Our reach extends to Googlers, Google Cloud customers, and billions of global users.

Develop comprehensive DFT strategies and architectures, including hierarchical DFT, high-speed I/O DFT, and analog DFT. Drive die-level DFT validation strategies and ensure complete Design Rule Checks (TDRC), implementing design changes to resolve violations and achieve high test quality. Implement essential DFT logic such as boundary scan, scan chains, DFT compression, Logic BIST, TAP controllers, and clock control blocks. Document the DFT architecture, test sequences, and boot-up sequences related to test pins. Generate and deliver production and debug patterns to the Post Silicon engineering team, providing diagnostic support for post-silicon phases.

A Bachelor's degree in Electrical Engineering or a related field, or equivalent practical experience, is required. A minimum of 8 years of experience in implementing and validating DFT technologies is essential. Proven experience across multiple projects in DFT design and verification, encompassing specification, definition, architecture, and insertion. Demonstrated expertise with various DFT techniques and tools, including ASIC DFT synthesis, simulation, and verification flows. Experience in leading DFT activities throughout an entire ASIC development lifecycle.

Preferred qualifications include a Master's degree or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field. Experience with IP integration for memories, test controllers, Test Access Points (TAP), and DFT for Multi-die SoCs is advantageous. Familiarity with fault modeling and SoC cycles, silicon bring-up, and silicon debug activities is a plus.