Shape the future of AI/ML hardware acceleration by driving cutting-edge TPU technology. You will be part of a team developing custom silicon solutions for Google's TPUs, contributing to products used by millions worldwide. Leverage your expertise in design and verification, focusing on TPU architecture and its integration within AI/ML-driven systems.

Google's computational challenges require custom hardware solutions. Your team designs and builds the foundational hardware, software, and networking technologies that power all of Google's services, from the lowest circuit design levels to large system implementations, seeing them through to high-volume manufacturing.

The AI and Infrastructure team redefines possibilities, empowering customers with breakthrough capabilities and insights through AI and Infrastructure at unparalleled scale, efficiency, reliability, and velocity. We drive Google's innovations, enabling cutting-edge AI models, delivering immense computing power to global services, and providing essential platforms for developers.

Define and architect Design for Testability (DFT) strategies, including hierarchical DFT and DFT for high-speed I/Os and analog components.

Develop and implement die-level DFT validation strategies, ensuring all Test Design Rule Checks (TDRC) are met and addressing violations to achieve superior test quality.

Integrate essential DFT logic such as boundary scan, scan chains, DFT compression, Logic BIST, TAP controllers, and clock control blocks.

Create comprehensive documentation for DFT architecture, test sequences, and boot-up sequences related to test pins.

Generate and deliver production and debug patterns to the Post Silicon engineering team, and conduct diagnosis for post-silicon support.

A Bachelor's degree in Electrical Engineering or a related field, or equivalent practical experience, is required.

Possess a minimum of 8 years of experience in the implementation and validation of DFT technologies.

Demonstrate experience with multiple projects involving DFT design, verification, specification, definition, architecture, and insertion.

Showcase expertise in DFT techniques and tools, including ASIC DFT synthesis, simulation, and verification flows.

Proven experience in leading DFT activities throughout the entire ASIC development lifecycle.