Shape the future of AI/ML hardware acceleration by contributing to cutting-edge TPU technology that powers Google's most demanding applications. Join a forward-thinking team developing custom silicon solutions for Google's TPUs, influencing products used by millions worldwide. Leverage your expertise in design and verification to ensure the integrity of complex digital designs, with a special focus on TPU architecture and its integration within AI/ML systems.

As a Design for Testing (DFT) micro-architect/design engineer, you'll support the core systems of Google's vast and powerful computing infrastructure. This role offers the opportunity to work across the entire development lifecycle, from initial circuit design to large-scale system development and high-volume manufacturing. Your contributions will directly impact the hardware powering our data centers, benefiting billions of Google users globally. The AI and Infrastructure team is at the forefront of innovation, empowering Google customers with breakthrough capabilities and insights through AI and Infrastructure delivered at unparalleled scale, efficiency, and reliability.

Develop and implement comprehensive DFT strategies and architectures, including hierarchical DFT, DFT for high-speed I/Os, and Analog DFT.

Drive the die-level DFT validation strategy, conduct thorough Test Design Rule Checks (TDRC), and implement necessary design changes to ensure high test quality.

Integrate essential DFT logic such as boundary scan, scan chains, DFT compression, Logic BIST, TAP controllers, and clock control blocks.

Create detailed documentation for DFT architecture, test sequences, and boot-up sequences related to test pins.

Generate and deliver production and debug patterns to the post-silicon engineering team, and perform diagnosis for post-silicon support.

A Bachelor's degree in Electrical Engineering, a related technical field, or equivalent practical experience is required.

Possess at least 8 years of experience in the implementation and validation of DFT technologies, including a strong track record across multiple projects in DFT design, verification, specification, definition, architecture, and insertion.

Demonstrate experience with a variety of DFT techniques and tools, coupled with proficiency in ASIC DFT synthesis, simulation, and verification flows.

Exhibit proven experience in leading DFT activities throughout the entire ASIC development lifecycle.

Preferred qualifications include a Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, along with experience in IP integration, fault modeling, and SoC silicon bringup and debug activities.