Shape the future of AI/ML hardware acceleration by driving cutting-edge TPU technology. Join a team pushing boundaries in custom silicon solutions for Google's most demanding AI/ML applications. Contribute to innovation behind globally loved products, leveraging design and verification expertise for complex digital designs, focusing on TPU architecture and its integration within AI/ML systems.

Our computational challenges demand in-house hardware solutions. Your role on the team designing and building hardware, software, and networking technologies will power all of Google's services. This position defines, designs, and analyzes the DFT implementation and flow that supports the world's largest and most powerful computing infrastructure.

The AI and Infrastructure team is redefining possibilities. We empower Google customers with breakthrough capabilities and insights through AI and Infrastructure at unparalleled scale, efficiency, reliability, and velocity. Our work is the driving force behind Google's groundbreaking innovations.

Develop comprehensive DFT strategies and architectures, including hierarchical DFT, DFT for high-speed I/Os, and Analog DFT. Drive die-level DFT validation strategy and ensure adherence to Test Design Rule Checks (TDRC), implementing necessary design changes for high test quality. Integrate essential DFT logic such as boundary scan, scan chains, DFT Compression, Logic BIST, TAP controllers, clock control blocks, and other DFT IP blocks. Create detailed documentation for DFT architecture, test sequences, and boot-up sequences related to test pins. Generate and deliver production and debug patterns to the Post Silicon engineering team, and perform diagnosis for post-silicon support.

A Bachelor's degree in Electrical Engineering or a related field, or equivalent practical experience, is essential. Requires 8 years of hands-on experience in implementing and validating DFT technologies. Demonstrated experience across multiple projects in DFT design and verification, including specification, definition, architecture, and insertion. Proficiency in DFT techniques and tools, along with experience in ASIC DFT synthesis, simulation, and verification flows. Proven experience leading DFT activities throughout the entire ASIC development lifecycle.