Join Google Cloud and shape the future of AI/ML hardware acceleration by working on cutting-edge TPU technology. You'll be instrumental in developing custom silicon solutions that power Google's most demanding AI/ML applications and contribute to innovative products used by millions worldwide. Leverage your expertise in design and verification to ensure the reliability of complex digital designs, focusing on TPU architecture and its integration within AI/ML systems.

Our computational needs are so unique that we engineer our own hardware. As part of a team responsible for Google's hardware, software, and networking technologies, you'll be at the forefront of innovation. Your work will directly impact the core infrastructure powering Google's vast services and influence the machinery within our advanced data centers, reaching countless Google users globally.

Develop and drive the overall DFT strategy and architecture, including hierarchical DFT and considerations for high-speed I/Os and analog components.

Establish and execute the die-level DFT validation strategy, ensuring all Test Design Rule Checks (TDRC) are met and resolving any violations to achieve superior test quality.

Implement essential DFT logic, such as boundary scan, scan chains, DFT compression, Logic BIST, TAP controllers, and other crucial DFT IP blocks.

Create comprehensive documentation for the DFT architecture, test sequences, and boot-up sequences related to test pins.

Generate and deliver production and debug patterns to the Post Silicon engineering team, and provide diagnostic support for post-silicon validation.

A Bachelor's degree in Electrical Engineering or a related field, or equivalent practical experience, is required.

Demonstrate at least 8 years of experience in implementing and validating DFT technologies.

Possess a proven track record of working on multiple projects involving DFT design, verification, specification, definition, architecture, and insertion.

Exhibit hands-on experience with various DFT techniques and tools, including ASIC DFT synthesis, simulation, and verification flows.

Showcase experience in leading DFT activities throughout the complete ASIC development lifecycle.

Preferred qualifications include a Master's degree or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.

Experience with IP integration, fault modeling, SoC cycles, silicon bring-up, and silicon debug activities is highly desirable.