Join Google Cloud as a Senior DFT Design Engineer and play a pivotal role in shaping the future of AI/ML hardware acceleration. You will drive TPU (Tensor Processing Unit) technology, powering Google's most demanding AI/ML applications. Be part of a team that pushes technological boundaries, developing custom silicon solutions for Google's TPUs.

This position offers the chance to contribute to innovations behind widely-used products. Leverage your design and verification expertise to validate complex digital designs, with a specific emphasis on TPU architecture and its integration within AI/ML-driven systems. You will help define and analyze the DFT implementation and flow, supporting the core systems of Google's massive computing infrastructure.

As a Senior DFT Design Engineer, you will be instrumental in developing the DFT strategy and architecture, encompassing areas like hierarchical DFT and DFT for high-speed I/Os and analog circuits. You will lead the die-level DFT validation strategy, ensuring comprehensive Test Design Rule Checks (TDRCs) and implementing necessary design changes to achieve superior test quality.

Key responsibilities include inserting essential DFT logic such as boundary scan, scan chains, compression, and logic BIST. You'll also manage TAP controllers and clock control blocks, along with other critical DFT IP blocks. Documenting the DFT architecture, test sequences, and boot-up sequences for test pins is also a core duty. Furthermore, you will generate and deliver production and debug patterns to the Post Silicon Engineering team, providing crucial support for post-silicon validation and diagnosis.

Candidates should possess a Bachelor's degree in Electrical Engineering, a related field, or equivalent practical experience. A minimum of 8 years of experience is required in implementing and validating Design for Testability (DFT) technologies. Proven experience across multiple projects is essential, covering DFT design and verification, specification, definition, architecture, and insertion.

Proficiency with DFT techniques and tools is a must, including experience with ASIC DFT synthesis, simulation, and the overall verification flow. Preferred qualifications include a Master's degree or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field. Experience in fault modeling, IP integration (e.g., memories, test controllers, TAP, and DFT for multi-die SoCs), and SoC cycles, silicon bring-up, and silicon debug activities is highly advantageous.