Shape the future of AI/ML hardware acceleration by driving cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. Join a team dedicated to developing custom silicon solutions and pushing the boundaries of AI/ML-driven systems. Leverage your design and verification expertise within a world-leading hyperscale computing environment, contributing to innovations that impact millions of users globally.

Define and architect DFT strategies, including hierarchical DFT and solutions for high-speed IOs and analog components. Drive die-level DFT validation, ensuring high test quality by addressing all Test Design Rule Checks (TDRC). Implement essential DFT logic such as boundary scan, scan chains, compression, logic BIST, TAP controllers, and clock control blocks. Document DFT architecture, test sequences, and associated boot-up protocols. Generate and deliver production/debug patterns for post-silicon support and conduct necessary diagnostics.

A Bachelor's degree in Electrical Engineering or a related field, or equivalent practical experience, is required, alongside 8 years of experience in implementing and validating DFT technologies. Proven experience across multiple projects in DFT design and verification, encompassing specification, definition, architecture, and insertion is essential. Familiarity with DFT techniques and tools, including ASIC DFT synthesis, simulation, and verification flows is necessary. A Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, or a related field, along with experience in fault modeling, IP integration, SoC cycles, silicon bring-up, and debug, is preferred.