Join Google Cloud as a Senior DFT Design Engineer and contribute to shaping the future of AI/ML hardware acceleration. You will play a key role in developing cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. Be part of a team pushing boundaries with custom silicon solutions for Google's TPU, impacting products used by millions worldwide. Leverage your design and verification expertise to ensure the integrity of complex digital designs, focusing on TPU architecture and its integration within AI/ML-driven systems.

This role offers the chance to define, design, and analyze DFT implementation and flows that are critical to the world's largest and most powerful computing infrastructure. Your work will span from the lowest levels of circuit design to large system development and high-volume manufacturing, directly influencing the machinery powering our data centers and affecting millions of Google users.

Develop and drive the DFT strategy and architecture, including hierarchical DFT, high-speed I/O DFT, and analog DFT. Define and execute the die-level DFT validation strategy, ensuring all Test Design Rule Checks (TDRC) are met and violations are resolved for optimal test quality.

Integrate essential DFT logic such as boundary scan, scan chains, DFT compression, logic BIST, TAP controllers, and clock control blocks. Document DFT architecture, test sequences, and boot-up sequences. Generate and deliver production and debug patterns for Post-Silicon Engineering and perform necessary diagnosis.

A Bachelor's degree in Electrical Engineering or a related field, or equivalent practical experience, is required. A minimum of 8 years of experience in implementing and validating DFT technologies is essential. Demonstrated experience across multiple projects in DFT design, verification, specification, architecture, and insertion is expected. Proficiency with DFT techniques and tools, including ASIC DFT synthesis, simulation, and verification flows, is necessary.

Preferred qualifications include a Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, or a related field. Experience in fault modeling, IP integration (memories, TAP, DFT for multi-die SoCs), and SoC cycles, silicon bring-up, and debug activities is highly advantageous.