Join a pioneering team shaping the future of AI/ML hardware acceleration. This role offers the chance to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You will be integral to a team pushing boundaries in custom silicon solutions for Google's TPUs, contributing to innovations that impact millions globally.

Leverage your design and verification expertise to ensure the integrity of complex digital designs, with a specialized focus on TPU architecture and its integration within AI/ML-driven systems. As a Senior DFT Design Engineer, you will define, design, and analyze DFT implementation and flows crucial for the world's largest and most powerful computing infrastructure. Your work will span from circuit design to large system development, seeing projects through to high-volume manufacturing and influencing the machinery within our data centers.

The AI and Infrastructure team is at the forefront of redefining possibilities, empowering Google customers with breakthrough capabilities and unparalleled scale, efficiency, reliability, and velocity. Our impact reaches Googlers, Google Cloud customers, and billions of users worldwide.

Develop comprehensive DFT strategies and architectures, including hierarchical DFT, DFT for high-speed I/Os, and Analog DFT. Drive the die-level DFT validation strategy and ensure all Test Design Rule Checks (TDRC) are met, implementing necessary design changes to achieve superior test quality. Integrate critical DFT logic, such as boundary scan, scan chains, DFT compression, logic BIST, TAP controllers, clock control blocks, and other essential DFT IP blocks. Create detailed documentation for DFT architecture, test sequences, and boot-up sequences associated with test pins. Generate and deliver production and debug patterns to the Post Silicon Engineering team, providing essential diagnosis for post-silicon support.

Requires a Bachelor's degree in Electrical Engineering or a related field, or equivalent practical experience. Possess 8 years of hands-on experience in the implementation and validation of DFT technologies. Demonstrate experience across multiple projects involving DFT design, verification, specification, definition, architecture, and insertion. Proficient in DFT techniques and tools, including ASIC DFT synthesis, simulation, and verification flows.

Preferred qualifications include a Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, or a related field. Experience in fault modeling, IP integration (e.g., memories, test controllers, TAP, DFT for multi-die SoCs), and SoC cycles, silicon bringup, and silicon debug activities is highly valued.